1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that executes an operational test of itself, in particular, to a semiconductor integrated circuit that includes different integrated circuit blocks mixed therein and which executes the operational test with respect to one of the mixed different integrated circuits. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-109086 filed on Apr. 1, 2004, which is herein incorporated by reference.
2. Description of the Related Art
A mixed circuit which includes a logic circuit and a memory circuit (for example, a Dynamic Random Access Memory (DRAM) circuit), or a system Large Scale Integrated (hereinafter referred to as “LSI”) circuit which includes different integrated circuits such as a DRAM, a Static Random Access Memory (SRAM), a Read only Memory (ROM) and a central Processing Unit (CPU) has been developed as a result of improvements made in design and manufacturing techniques.
The above-mentioned circuit may include an internal circuit that is externally accessed through another circuit during a normal operational mode of the circuit. FIG. 1 is a block diagram for describing a logic memory mixed circuit 700A of the related art. The logic memory mixed circuit 700A includes a memory circuit 710A that is coupled to external input-output pads 730 through a logic circuit 720A. That is, an external input signal is initially input to the logic circuit 720A and then an internal input signal generated by the logic circuit 720A is transferred to an internal input terminal of the memory circuit 710A. Likewise, an internal output signal generated by the memory circuit 710A is transferred to the external input-output pad 730 through the logic circuit 720A. When an operational test is executed only against the memory circuit 710A, an external test signal received by the external input-output pad 730 needs to be directly provided to the memory circuit 710A.
FIG. 2 is a circuit block diagram for describing a semiconductor integrated circuit 700B of another related art. The semiconductor integrated circuit 700B includes a logic circuit 720B coupled between external input pads 731 through 733 and internal input terminals 711 through 713 of a memory circuit 710B. The logic circuit 720B includes a plurality of sub-logic circuits 721 coupled with each other by interconnections 722. In order to provide external test signals eTCK, eTWE and eTRE directly to the memory circuit 710B, the logic circuit 720B includes selection circuits. The external test signals can be directly provided to the memory circuit 710B without passing through the sub-logic circuits 721 of the logic circuit 720B by switching the selection circuits.
However, in the semiconductor integrated circuit 700B as shown in FIG. 2, the number of the sub-logic circuits 721 and the length of the interconnections 722 between the external input pads 731 through 733 and the internal input terminals 711 through 713 are different than each other. For example, the number of the sub-logic circuits 721 between the external input pads 731 and the internal input terminals 711 is different than the number of sub-logic circuits 721 between the external input pads 732 and the internal input terminals 712. Also, the length of the interconnection between the external input pads 731 and the internal input terminals 711 is different than the length of the interconnection between the external input pads 732 and the internal input terminals 712. Thus, delay times caused by the logic circuit 720B may be different among the external test signals eTCK, eTWE and eTRE. Therefore, even though the external test signals eTCK, eTWE and eTRE are input to the external input pads 731 through 733 in accordance with a desired input timing of signals in the memory circuit 710B, internal test signals iTCK, iTWE and iTRE generated by the logic circuit 720B may not be provided to the memory circuit 710B in accordance with the desired input of signals in the memory circuit 710B. That is, there are different delay times among the internal test signals iTCK, iTWE and iTRE. As a result, the operational test may not be properly executed in the memory circuit 710B of the semiconductor integrated circuit 700B. In order to suppress the disadvantage with respect to the operational test, the external test signals eTCK, eTWE and eTRE may be input to the external input pads 731 through 733 previously with the different delay times of the internal test signals iTCK, iTWE and iTRE. Therefore, it is necessary that the different delay times of the internal test signals iTCK, iTWE and iTRE are exactly measured to improve the reliability of the operational test.
The following first and second measuring techniques for the delay times of the external test signals are disclosed.
The delay times of the external test signals are directly measured using a needle pico-probe and an oscilloscope in the first measuring technique. In this technique, after the needle pico-probes contact the external input pads 731 through 733 and the internal input terminals 711 through 713, voltage waveforms of the external input pads 731 through 733 and the internal input terminals 711 through 713 are detected by the oscilloscope. Then, the delay times of the external test signals can be obtained based on the voltage waveforms.
Also, the second measuring technique is described in a Patent Document 1 (Japanese Patent Publication Laid-open No. 2001-153930), in particular, in the paragraph [0036] through [0042] of the Document 1. In the second measuring technique, interconnections are constructed so that the external test signals input to test signal input pads can be output from test signal output pads through an under-test circuit (for example, the memory circuit 710B) as test result signals. Then, the delay times of the test result signals are measured. As a result, the delay times of the external test signals can be obtained.
However, in the first measuring technique, an operator needs to manually make the needle pico-probe contact the external input pads 731 through 733 and the internal input terminals 711 through 713, and it takes a long time for the operational test to be executed. Furthermore, it is hard for the operator to execute the operational test under a condition of high temperature. Therefore, the measurement results may not be always correct. Also, in the second measuring technique, a large-scaled test circuit (the test control circuit 5 described in the Document 1) and test interconnections (the test bus 2 described in the Document 1) need to be used for the operational test. Therefore, the size of the semiconductor integrated circuit becomes large.
Meanwhile, consumption current of the semiconductor integrated circuit may be measured in the operational test. For example, the following consumption current measuring technique is disclosed as the related art in a Patent Document 2 (Japanese Patent Publication Laid-open No. 2003-256495). In this measuring technique, the consumption current of the semiconductor integrated circuit is detected using an RT radioimmunoassary test and test patterns. However, the consumption current only in the memory circuit 710B as described in FIG. 1 may not be detected by the consumption current measuring technique described in the Document 2.